JP-A-H9-237131 discloses a technology for reducing power consumptions of peripheral circuits built-in in a semiconductor integrated circuit device (IC). The IC includes an access detection circuit for detecting accesses made by a CPU to each of the peripheral circuits and outputting a clock enable signal in the event of a detected access to any specific one of the peripheral circuits. This IC further includes a clock control circuit for supplying a main clock signal to an internal circuit of the specific peripheral circuit for a period of time long enough for completing an operation carried out by the internal circuit since an operation carried out by the access detection circuit to output the clock enable signal.
A clock-synchronized serial communication unit is one of the peripheral circuits. In general, a host microcomputer external to the IC transmits a communication clock signal and serial data to the serial communication unit. A receiving shift register employed inside the serial communication unit receives the serial data synchronously with the communication clock signal. After being temporarily stored in the receiving shift register, the serial data is processed inside the IC synchronously with a system clock signal generated internally in the IC. An operation to transmit data is carried out in the same way as this operation to receive data.
In the mean time, attempts are being made to reduce power consumptions of recent ICs. A recent IC is typically provided with a function to make a transition to a low power consumption mode (or a sleep operating mode) in which, after the lapse of a predetermined period of time or after completion of a predetermined process, for example, all internal clock signals of the IC are stopped till next serial data is received. Once the operation of an oscillation circuit for generating a system clock signal is stopped, however, it will take several milliseconds to several hundreds of milliseconds as a period of time to wait for the oscillation to become stable at the time the oscillation circuit resumes the oscillation. Examples of the oscillation circuit are a ceramic oscillation circuit, a CR oscillation circuit and a crystal oscillation circuit. The waiting period of time causes an inability to resume the communication immediately.
In order to solve this problem, instead of stopping all clock signals, a typical technique is proposed to allow only the oscillating operation of the CR oscillation circuit to continue and to process received data by using a clock signal generated by the CR oscillation circuit. If the IC is employed in for example an electronic control apparatus mounted on a vehicle, however, the continuation of the operation of even the CR oscillation circuit only is not a desirable technique for reducing the power consumption of the IC. This is because the driver often leaves the vehicle unused for a long time.
In addition, as another means, there is also conceived a configuration in which, after an external host microcomputer transmits serial data of 1 frame along with a communication clock signal to the IC, the microcomputer subsequently transmits an operation-use dummy communication clock signal to the IC to be utilized by the IC as a signal for processing the received serial data. The dummy communication clock signal is thus not used for synchronization of the communication for originally transmitting the serial data, but serves as a substitute for the system clock signal, which must otherwise be generated internally by the IC, to give timings for processing the received serial data.
By adoption of this other means, however, serial data cannot be transmitted continuously. Thus, the communication speed decreases and, in addition, the size of a program executed by the host microcomputer increases and control implemented by the microcomputer also becomes complicated because the microcomputer must transmit the extra dummy clock signal to be used by the IC to carry out the operation of processing the received serial data.